The present invention relates generally to phase change memory cells, and more specifically, to phase change memory cells suitable for high temperature operation.
Phase change material has a variety of applications in microelectronic devices such as optical storage media and solid state phase change memory devices. Phase change random access memory (PRAM) devices, for example, store data using a phase change material, such as, for example, a chalcogenide alloy, that transforms into a crystalline state or an amorphous state during cooling after a heat treatment. Each state of the phase change material has different resistance characteristics. Specifically, the phase change material in the crystalline state has low resistance and the phase change material in the amorphous state has high resistance. The crystalline state is typically referred to as a “set state” having a logic level “0”, and the amorphous state is typically referred to as a “reset state” having a logic level “1”. A current passed through the phase change material creates ohmic heating and causes the phase change material to melt. Melting and gradually cooling down the phase change material allows time for the phase change material to form the crystalline state. Melting and abruptly cooling the phase change material quenches the phase change material into the amorphous state. High resistance values are likely to change at high temperatures due to crystallization. Material with high crystallization temperature is more suitable for higher temperature operation. However, once quenched, the crystallization temperature decreases and the amorphous region is surrounded by a crystalline layer which acts as a seed for growth as shown in FIG. 1, for example.
FIG. 1 is a diagram illustrating a pillar phase change memory cell operating in the reset state at nominal operating conditions. As shown in FIG. 1, a pillar phase change memory cell 100 includes a bottom electrode 102, a pillar 104 filled with phase change material, and a top electrode 106. The bottom electrode 102 is formed on a conductive contact 108. Insulation material 110 and 111 surrounds the bottom electrode 102, the pillar 104, the top electrode 106 and the conductive contact 108. As shown in FIG. 1, after the reset operation is performed, a crystalline region 104a remains and surrounds an amorphous region 104b and acts as a seed for nucleation and crystal growth. Thus, if the phase change memory cell 100 is raised to a higher temperature, the data stored within the memory cell 100 may be lost or degraded due to changes in the size and shape of the amorphous region 104b. 